1. Field of the Invention
The present invention relates to a semiconductor device including a circuit having a multilayer wiring structure and, more specifically, to a system LSI to be designed using an IP (intellectual property) core.
2. Description of the Related Art
With development of a fine device structure and a high integration density of a semiconductor device according to progress of process technology,
a system LSI including a plurality of function blocks (circuits) in or on one chip has recently been achieved. In this system LSI, a general-purpose function block is efficiently designed reusing an IP core (design core) that is past design resources.
FIG. 7 shows a semiconductor memory chip using an SRAM (Static Random Access read write Memory) as an example of a system LSI.
In the case of the semiconductor chip 100, when the device is designed, part of the device logic section 102 is designed using an SRAM design core 101 that is an IP core. Therefore, the development and design can be effectively carried out.
However, the system LSI includes various types of function blocks according to the specification of the device (product). For example, some function blocks have a four-level wiring structure and other function blocks have a five-level wiring structure. Further, some function blocks having the same number of wiring layers include a thick wiring layer like a function block whose uppermost wiring layer serves as a power line or a high-speed signal line.
For the reasons described above, conventionally, IP cores must be prepared for every each type of function blocks in order to improve efficiency of the design of the system LSI.
FIGS. 8A and 8B show an example of a system LSI in which two different function blocks IP1 and IP2 are provided on a single chip. FIG. 8A is a plan view of the chip and FIG. 8B is a cross-sectional view showing a main part (wiring layers) of the chip.
Referring to FIGS. 8A and 8B, the function block IP1 corresponding to an IP core IP1a includes a four-level layer structure having four wiring layers M1 to M4. It is seen from FIG. 8B that the wiring layers M1 to M4 have the same wiring pitch and the same thickness (thin wiring layers).
At the time of designing the system LSI, the IP core IP1a having wiring data for forming each of the wiring layers M1 to M4 is read out from a library and used, as illustrated in FIGS. 9A and 9B.
As shown in FIG. 10B, the function block IP2 corresponding to an IP core IP2a includes a four-level layer structure having four wiring layers M1 to M4. The wiring layers M1 to M3 in these wiring layers M1 to M4 have the same wiring pitch and the same thickness (thin wiring layers).
The wiring pitch of the uppermost wiring layers M4 is wider than the wiring layers M1 to M3 and each of the wiring layers M4 is thicker than each of the wiring layers M1 to M3. Each of the thick uppermost wiring layers M4 is used as the power supply line, the signal line or the like.
At the time of designing the system LSI, the IP core IP2a having wiring data for forming each of the wiring layers M1 to M4 is read out from the library and used, as illustrated in FIG. 10A.
FIGS. 11A and 11B show an example of a system LSI in which three different function blocks IP3, IP4 and IP5 are provided on a single chip. FIG. 11A is a plan view of the chip and FIG. 11B is a cross-sectional view showing a main part (wiring layers) of the chip.
Referring to FIG. 11A, the function block IP3 corresponding to an IP core IP3a is formed to include a five-level layer structure having five wiring layers M1 to M5. It is seen from FIG. 11B that the wiring layers M1 to M5 have the same wiring pitch and the same thickness (thin wiring layers).
The function block IP4 corresponding to an IP core IP4a includes a five-level layer structure having five wiring layers M1 to M5. The wiring layers M1 to M4 in these wiring layers M1 to M5 have the same wiring pitch and the same thickness (thin wiring layers), as is seen from FIG. 11B.
The wiring pitch of the uppermost wiring layers M5 is wider than the wiring layers M1 to M4 and each of the wiring layers M5 is thicker than each of the wiring layers H1 to M4. Each of the thick uppermost wiring layers M5 is used as the power supply line, the signal line or the like.
The function block IP5 corresponding to an IP core IP5a includes a four-level layer structure having four wiring layers M1 to M4. The wiring layers M1 to M3 in these wiring layers M1 to M4 have the same wiring pitch and the same thickness (thin wiring layers), as is seen from FIG. 11B.
The wiring pitch of the uppermost wiring layers M4 is wider than the wiring layers M1 to M3 and each of the wiring layers M4 is thicker than each of the wiring layers M1 to M3. Each of the thick uppermost wiring layers M4 is used as the power supply line, the signal line or the like.
In this case, also, the IP core IP3a for forming each of the wiring layers M1 to M5 of the function block IP3, the IP core IP4a for forming each of the wiring layers M1 to M5 of the function block IP4, and the IP core IP5a for forming each of the wiring layers M1 to M4 of the function block IP5 are stored in the library.
As described above, an IP core adapted to the type of the function block (more specifically the structure of wiring layers) is read out from the library and used to design a general-purpose function block to be formed on a chip. Therefore, it is necessary to prepare IP cores for every each function block of different type in order to design the function blocks with efficiency.
Therefore, general-purpose function blocks can be efficiently designed reusing IP cores. However, there is a problem that PI cores are prepared for each of function blocks of different types.